# Settling time

## Settling time to n-bits

The relative settling error versus time can be founs as:

$$\mathrm{\epsilon}_{s}=1.0\,{\mathrm{e}}^{-\frac{1.0\,t}{C\,R}}$$

The settling time to $n$ bit can be found as the solution of:

$$\mathrm{\epsilon}_{s}=\frac{1}{{2.0}^{1.0\,n}}$$

This yields:

$$\mathrm{\tau}_{s}=-1.0\,C\,R\,\ln\left(\frac{1}{{2.0}^{1.0\,n}}\right)$$

## Component design equations

The resistance $R$ can be written as a function of the capacitance $C$ and the settling time $\tau_s$ to $n$ bit:

$$R=-\frac{1.0\,\mathrm{\tau}_{s}}{C\,\ln\left(\frac{1}{{2.0}^{1.0\,n}}\right)}$$

The capacitance $C$ can be written as a function of the resistance $R$ and the settling time $\tau_s$ to $n$ bit:

$$C=-\frac{1.0\,\mathrm{\tau}_{s}}{R\,\ln\left(\frac{1}{{2.0}^{1.0\,n}}\right)}$$

## Numeric example

For a settling time of 100ns to 10bit, with a capacitance of 10pF, we need a resistance of: 1442.695$\Omega$

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SLiCAP: Symbolic Linear Circuit Analysis Program, Version 0.5 © 2009-2018 Anton Montagne